-- PRAGMA standard control signal mapping:
-- clk								=> clk
-- clk_48k							=> clk_48k
-- reset								=> reset
-- PAY ATTENTION:					RESET IS ACTIVE LOW
-- control_in	(0) 				=> chorus_enable
--					(7 downto 1) 	=> UNUSED
--
--	control_out	(0)				<= enable
--					(3 downto 1)	<= UNUSED
-- 
-- PCM_data_in_right				=> PCM_data_in_right
-- PCM_data_in_left				=> PCM_data_in_left
-- PCM_data_out_right			<= PCM_data_out_right
-- PCM_data_out_left				<= PCM_data_out_left

library ieee;
use ieee.std_logic_signed.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use work.delay_pkg.all;

entity PRM_time_1 is
  port(
    clk				: in std_logic;
	 clk_48k			: in std_logic;
    reset			: in std_logic;
	 
	 control_in		: in std_logic_vector(7 downto 0);
	 control_out	: out std_logic_vector(3 downto 0);
	 
    PCM_data_in_right	: in std_logic_vector(15 downto 0);
	 PCM_data_in_left		: in std_logic_vector(15 downto 0);
    PCM_data_out_right	: out std_logic_vector(15 downto 0);
	 PCM_data_out_left	: out std_logic_vector(15 downto 0)
    );
end entity PRM_time_1;

architecture structural of PRM_time_1 is
  component delay is
    generic(
		G0							: integer;
		G1							: integer;
		G2							: integer;
		G3							: integer);
	 port(
      clk						: in std_logic;
		clk_48k					: in std_logic;
      reset						: in std_logic;
		
		control_in				: in std_logic_vector(7 downto 0);
		control_out				: out std_logic_vector(3 downto 0);
		
      PCM_data_in				: in std_logic_vector(15 downto 0);
		PCM_data_out			: out std_logic_vector(15 downto 0)
      );
  end component delay;
  
  signal reverb_enable			: std_logic;
  
  signal control_in_left		: std_logic_vector(7 downto 0);
  signal control_out_left_0	: std_logic_vector(3 downto 0);
  signal control_out_left_1	: std_logic_vector(3 downto 0);
  signal control_out_left_2	: std_logic_vector(3 downto 0);
  signal control_out_left_3	: std_logic_vector(3 downto 0);
  
  signal PM_data_0				: std_logic_vector(15 downto 0);
  signal PM_data_1				: std_logic_vector(15 downto 0);
  signal PM_data_2				: std_logic_vector(15 downto 0);
  signal PM_data_3				: std_logic_vector(15 downto 0);
   
begin

	reverb_enable	<= control_in(0);
	
	control_out(0)	<= reverb_enable;
	control_out(1)	<= control_in(1);
	control_out(2)	<= control_in(2);
	control_out(3)	<= control_in(3);
	
	pitch_mod_0_left: delay generic map(
											G0						=> 10,
											G1						=> 1389,
											G2						=> 692,
											G3						=> 1023)							
									port map (	
											clk 					=> clk,
											clk_48k				=> clk_48k,
											reset 				=> reset,
								
											control_in			=> control_in_left,
											control_out			=> control_out_left_0,

											PCM_data_in			=> PCM_data_in_left,
											PCM_data_out		=> PM_data_0
											);
											
	pitch_mod_1_left: delay generic map(
											G0						=> 1561,
											G1						=> 1289,
											G2						=> 792,
											G3						=> 1023)							
									port map (	
											clk 					=> clk,
											clk_48k				=> clk_48k,
											reset 				=> reset,
								
											control_in			=> control_in_left,
											control_out			=> control_out_left_1,

											PCM_data_in			=> PCM_data_in_left,
											PCM_data_out		=> PM_data_1
											);
											
	pitch_mod_2_left: delay generic map(
											G0						=> 520,
											G1						=> 1489,
											G2						=> 592,
											G3						=> 1023)							
									port map (	
											clk 					=> clk,
											clk_48k				=> clk_48k,
											reset 				=> reset,
								
											control_in			=> control_in_left,
											control_out			=> control_out_left_2,

											PCM_data_in			=> PCM_data_in_left,
											PCM_data_out		=> PM_data_2
											);
  
  p_left: process(clk, reset)
  begin
    if (reset = '0') then                   --RESET ACTIVE LOW
      PCM_data_out_left 	<= (others => '0');
		PCM_data_out_right 	<= (others => '0'); 
    elsif (clk'event and clk = '1') then    --POSIVITE EDGE
		if (reverb_enable = '1') then
			PCM_data_out_left <= shr(PCM_data_in_left,"010") 
										+ shr(PM_data_0,"010")
										+ shr(PM_data_1,"010")
										+ shr(PM_data_2,"010");
		else
			PCM_data_out_left <= PCM_data_in_left;
		end if;
	 end if;
  end process;

end architecture structural;
